Compilation

The compiler takes a quantum circuit and a device, and writes the programme the device runs: which ion holds each qubit, how ions are carried so that the two ions of every two-qubit gate stand in the same trap, and the laser operations, in order. Every example on this page can be played.

Every programme it writes is checked twice: against the rules of the machine, and against the circuit, to show that it computes what the circuit says.

The input, and the machine's three operations

The input is a circuit in OpenQASM 2.0, the standard text format for quantum circuits (its specification). A trapped-ion machine cannot apply most of its gates directly. This one has three operations, and every gate is rewritten into them:

operationacts onwhat it doesas a matrix
R(θ, φ)one ionOne laser pulse. It rotates the qubit by the angle θ about an axis lying in the X–Y plane, at the angle φ from X: φ = 0 is a rotation about X, φ = π/2 about Y. Written Rx(θ) and Ry(θ) for those two.cos(θ/2)·I − i sin(θ/2)·(cos φ·X + sin φ·Y)
VZ(λ)one ionA rotation by the angle λ about Z, the one axis an R pulse cannot turn about.diag(1, eiλ)
MS(θ)two ions in one trapOne laser pulse reaching both ions, which entangles the two qubits by the angle θ. It is the only way two qubits interact here, which is why the two ions of a two-qubit gate must first be carried into the same trap.cos(θ/2)·I − i sin(θ/2)·X⊗X

What a VZ costs. On a machine that can set the phase of the laser reaching each ion on its own, a rotation about Z is free: no laser fires, and the phase of that ion's later pulses is shifted instead. Here the beams are shared between ions, so the rotation has to be made with pulses: Rx(π/2)·Ry(λ)·Rx(−π/2), three R pulses (the rightmost first), equals VZ(λ) up to a global phase. The programme still writes it as one VZ, and the clock charges it the time of three pulses, unless the device declares a gate that turns about Z in one pulse.

The two identities every gate is rewritten by. Each is proved, so the operations written for a gate are that gate (the rightmost factor happens first):

u3(θ, φ, λ) = VZ(φ + λ) · R(θ, π/2 − λ)
CX = e−iπ/4 · [Ry(−π/2) ⊗ I] · [Rx(−π/2) ⊗ Rx(−π/2)] · MS(π/2) · [Ry(π/2) ⊗ I]

The first says any single-qubit gate is one pulse followed by one rotation about Z: u3 is OpenQASM's general single-qubit gate, and every named one is a u3 with fixed angles (h is u3(π/2, 0, π), t is u3(0, 0, π/4)). The second says a CNOT is one MS between four single-ion pulses. That the operations which actually fire are the ones for the gate you wrote is checked separately, by composing them back into the circuit (R10, below).

what you writewhich gateswhat the machine does
single-qubit
19 gatesid x y z h s sdg t tdg sx sxdg rx ry rz u1 p u2 u3 u
one R pulse, then one VZ
two-qubit
7 gatescx cz cy ch swap cu1 cp
cx is one MS(π/2) between four R pulses; the others are cx with single-qubit gates around it
three-qubit
1 gatesccx
the standard decomposition into six CNOTs and single-qubit gates
non-unitary
3 gatesmeasure reset barrier
readout and preparation, in a trap equipped for them; a barrier only orders, and costs nothing
OPENQASM 2.0;
include "qelib1.inc";
qreg q[2];
creg c[2];
h q[0];
cx q[0],q[1];
measure q -> c;
the same circuit, drawn
q0q1H

How a circuit becomes a machine programme

In short: read the circuit, rewrite every gate as the machine's operations, decide which ion plays which qubit, carry ions so that the pairs that must interact end up in the same trap, write out the instructions, add cooling where the ions would be too hot to gate — then check the result, twice. The nine steps below are that in full.

  1. Read the circuitthe operations, and the order between them
    the circuit becomes a list of operations, each with its qubits and its angles. Between them the compiler keeps the dependency graph: an arrow from each operation to the next one that uses the same qubit. An operation may run only after everything with a path of arrows to it; two operations with no path between them may run in either order, or at the same time.
  2. Rewritenative operations for each gate
    every gate becomes the machine's operations by the two identities above: a single-qubit gate is one R and one VZ, a CNOT one MS between four R pulses, and a gate on three qubits (a Toffoli) is first unfolded into one- and two-qubit gates.
  3. Placewhich ion is which qubit, and where it starts
    each qubit is given an ion, and each ion a starting trap, so that qubits that gate together start close together (how, in §3).
  4. Route and schedulethe moves, in layers
    operations run in layers of the dependency graph, and each qubit's operations keep the circuit's order exactly, even where two of them would commute. Before a two-qubit gate, its two ions are carried to one trap that can gate: one hop at a time on most devices, or, on a ring more than about half full, by turning the whole ring at once. This is this website's compiler. The papers on Reproduce use their own compilers, with their own ways of routing ions; there, each paper's schedules are replayed as its own code wrote them, and ours are set beside them under the same rules.
  5. Write outthe programme, and its certificate
    the programme is one instruction per step, each marked with the operation of the circuit it carries out. Beside it the compiler writes a certificate: which ion is which qubit, where each ion starts, every move, and one witness per gate. A witness is the compiler's claim about one gate of the circuit: it happens at instruction k, in trap T, on ions a and b. The checks below test every claim instead of trusting it.
  6. Coolcooling where it is needed
    the programme is replayed with the device's heating model, and a cooling operation is added wherever a gate would otherwise start on ions too hot to gate (R7).
  7. Check the rulesevery rule of the rule set
    the cooled programme is replayed and every rule of the rule set is evaluated on it, exactly as on the Rules page: the standard rule set, unless the compiler was given another.
  8. Check what it computesR10, in two halves
    O1, where every gate happens: the certificate's moves are replayed from the starting positions; every witness must name exactly the ions its gate's qubits are mapped to and find them together in a trap that can gate, every move must be one the device allows, and every gate of the circuit must be witnessed once, in the circuit's order on each of its qubits. O1 is decided by a checker whose correctness is proved, and which reads the device from its description, not from the compiler. O2, what the gates compute: the pulses are read out of the programme, composed through the qubit-to-ion map, and compared with the circuit as written, each measurement and reset in its place. A circuit of Clifford gates (H, S, CNOT and the Pauli gates, with measurement) is compared as a stabilizer tableau, whose size grows only with the square of the number of qubits, so circuits of any size are checked. Outside them (a T gate, an arbitrary angle) the exact matrices are compared, and those grow as 4n: up to 10 qubits, counting one more for each measurement in the middle of the circuit. Beyond that O2 is reported as not checked, never as passing. O2 is computed, not proved; it is the half that says which gates the programme applies.
  9. Drawthe page
    the page joins the programme and the circuit through the marks on the instructions, after checking each witness against the instruction it names; a disagreement refuses to draw.

The ion mapping, verified

For the Bell pair, compiled here onto the four-site register, each qubit is given an ion and a starting trap. The CNOT needs both ions in one trap, and that happens in two steps: one ion is carried along the register until its trap sits right beside the other — the ion waiting there does not move — and then the two traps are merged into one. The waiting ion shifts by a couple of micrometres as the merge completes, against the hundreds it would move if it were the one being carried. The check recomputes every position from the starting positions and the list of moves, and checks that each gate's ions are where its witness says.

qubitionstartsends
q0q0C1C0
q1q1C0C0

moves recorded: q0 C1→C0

#0   init q0@C1, q1@C0
#1   cool all
#2   gate R q0 @C1   ← op 0 h
#3   gate VZ q0 @C1   ← op 0 h
#4   shuttle q0 C1→C0   ← op 1 cx
#5   gate R q0 @C0   ← op 1 cx
#6   gate MS q0,q1 @C0   ← op 1 cx
#7   gate R q0 @C0   ← op 1 cx
#8   gate R q1 @C0   ← op 1 cx
#9   gate R q0 @C0   ← op 1 cx
#10  measure q0,q1   ← op 2 measure, 3 measure

The pulse sequence, matched to the gate

Each witness names the instruction that completes the gate, the trap, the ions and the operations, in the order they happen. Two checks meet here: the identities above say these operations are this gate, and O2 composes the operations the programme actually fires back into the circuit, so an operation that fires without a witness, or a witness without its operation, is caught.

op 0 (h) at C1, instruction #3: R(1.5708,-1.5708)@q0, VZ(3.14159)@q0op 1 (cx) at C0, instruction #9: R(1.5708,1.5708)@q0, MS(1.5708)@q0,q1, R(-1.5708,0)@q0, R(-1.5708,0)@q1, R(-1.5708,1.5708)@q0

Verdict for the Bell pair: 28 rules hold, R7 fail; R10 holds — O1 accepted by the proved checker; O2 by stabilizer tableau, composed from the emitted pulses, against the circuit as written.

runs

The compiled Bell pair on the four-site register: press Play, or step it. The full page shows the circuit stepping beside the programme.

open the page

Every basic gate, compiled and verified

One circuit per gate, each on one of four small devices named on its card, through the same steps: the input, the programme it became, the ion mapping, the operations witnessed, and the verdicts of the rules and of R10's two halves. The two-qubit gates show the transport that brings the ions together; the gates outside the Clifford set (t, and the rotations by an arbitrary angle) are compared as exact matrices.

h q[0]; a half turn about the diagonal axis: one turn about z, then one pulse

device: chain4, a four-site linear register C0–C3, every site a trap, no junctions

the circuit
q0q1H
input
h q[0];
ion mapping
qubitionstartsends
q0q0C1C1
q1q1C0C0
pulses witnessed
op 0 at C1: R(1.5708,-1.5708)@q0, VZ(3.14159)@q0
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (4 instructions, cooled)
#0   init q0@C1, q1@C0
#1   cool all
#2   gate R q0 @C1   ← op 0 h
#3   gate VZ q0 @C1   ← op 0 h

x q[0]; a bit flip: 0 and 1 swap over. One pulse

device: race8, an eight-site racetrack S0–S7: one loop of trap sites, no junctions

the circuit
q0q1X
input
x q[0];
ion mapping
qubitionstartsends
q0q0S0S0
q1q1S1S1
pulses witnessed
op 0 at S0: R(3.14159,-1.5708)@q0, VZ(3.14159)@q0
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (4 instructions, cooled)
#0   init q0@S0, q1@S1
#1   cool all
#2   gate R q0 @S0   ← op 0 x
#3   gate VZ q0 @S0   ← op 0 x

y q[0]; a bit flip with a phase: one pulse, about a different axis

device: grid2x3, a 2×3 lattice: T-junctions and corners, one trap on every wire

the circuit
q0q1Y
input
y q[0];
ion mapping
qubitionstartsends
q0q0T0_1hT0_1h
q1q1T0_0hT0_0h
pulses witnessed
op 0 at T0_1h: R(3.14159,0)@q0, VZ(3.14159)@q0
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (4 instructions, cooled)
#0   init q0@T0_1h, q1@T0_0h
#1   cool all
#2   gate R q0 @T0_1h   ← op 0 y
#3   gate VZ q0 @T0_1h   ← op 0 y

z q[0]; a phase flip: a half turn about z. Free on some machines, three pulses on this one

device: ring6d, the six-site ring with two dock spurs

the circuit
q0q1Z
input
z q[0];
ion mapping
qubitionstartsends
q0q0A0A0
q1q1A3A3
pulses witnessed
op 0 at A0: R(0,-1.5708)@q0, VZ(3.14159)@q0
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (4 instructions, cooled)
#0   init q0@A0, q1@A3
#1   cool all
#2   gate R q0 @A0   ← op 0 z
#3   gate VZ q0 @A0   ← op 0 z

s q[0]; a quarter turn about z: three pulses here, for the same reason as z

device: chain4, a four-site linear register C0–C3, every site a trap, no junctions

the circuit
q0q1S
input
s q[0];
ion mapping
qubitionstartsends
q0q0C1C1
q1q1C0C0
pulses witnessed
op 0 at C1: R(0,0)@q0, VZ(1.5708)@q0
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (4 instructions, cooled)
#0   init q0@C1, q1@C0
#1   cool all
#2   gate R q0 @C1   ← op 0 s
#3   gate VZ q0 @C1   ← op 0 s

t q[0]; an eighth of a turn about z. The check for this one compares the exact rotation, not a shortcut

device: race8, an eight-site racetrack S0–S7: one loop of trap sites, no junctions

the circuit
q0q1T
input
t q[0];
ion mapping
qubitionstartsends
q0q0S0S0
q1q1S1S1
pulses witnessed
op 0 at S0: R(0,0.785398)@q0, VZ(0.785398)@q0
verdict · exact 4x4 unitary, built from the emitted pulses, against the circuit as written; global phase +0.0000
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok (max entry error 1.57e-16)
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (4 instructions, cooled)
#0   init q0@S0, q1@S1
#1   cool all
#2   gate R q0 @S0   ← op 0 t
#3   gate VZ q0 @S0   ← op 0 t

rx(0.5) q[0]; any angle at all, about x: one pulse

device: grid2x3, a 2×3 lattice: T-junctions and corners, one trap on every wire

the circuit
q0q1Rx(0.5)
input
rx(0.5) q[0];
ion mapping
qubitionstartsends
q0q0T0_1hT0_1h
q1q1T0_0hT0_0h
pulses witnessed
op 0 at T0_1h: R(0.5,0)@q0, VZ(0)@q0
verdict · exact 4x4 unitary, built from the emitted pulses, against the circuit as written; global phase +0.0000
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok (max entry error 0.00e+00)
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (4 instructions, cooled)
#0   init q0@T0_1h, q1@T0_0h
#1   cool all
#2   gate R q0 @T0_1h   ← op 0 rx
#3   gate VZ q0 @T0_1h   ← op 0 rx

ry(0.5) q[0]; any angle at all, about y: one pulse

device: ring6d, the six-site ring with two dock spurs

the circuit
q0q1Ry(0.5)
input
ry(0.5) q[0];
ion mapping
qubitionstartsends
q0q0A0A0
q1q1A3A3
pulses witnessed
op 0 at A0: R(0.5,1.5708)@q0, VZ(0)@q0
verdict · exact 4x4 unitary, built from the emitted pulses, against the circuit as written; global phase +0.0000
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok (max entry error 1.51e-17)
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (4 instructions, cooled)
#0   init q0@A0, q1@A3
#1   cool all
#2   gate R q0 @A0   ← op 0 ry
#3   gate VZ q0 @A0   ← op 0 ry

rz(0.7854) q[0]; any angle about z, which this machine pays for in pulses

device: chain4, a four-site linear register C0–C3, every site a trap, no junctions

the circuit
q0q1Rz(0.79)
input
rz(0.7854) q[0];
ion mapping
qubitionstartsends
q0q0C1C1
q1q1C0C0
pulses witnessed
op 0 at C1: R(0,0.785396)@q0, VZ(0.7854)@q0
verdict · exact 4x4 unitary, built from the emitted pulses, against the circuit as written; global phase +0.3927
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok (max entry error 1.12e-16)
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (4 instructions, cooled)
#0   init q0@C1, q1@C0
#1   cool all
#2   gate R q0 @C1   ← op 0 rz
#3   gate VZ q0 @C1   ← op 0 rz

cx q[0],q[1]; the entangler: carry one ion to the other, then one two-ion pulse with four single-ion pulses around it

device: grid2x3, a 2×3 lattice: T-junctions and corners, one trap on every wire

the circuit
q0q1
input
cx q[0],q[1];
ion mapping
qubitionstartsends
q0q0T0_1hT0_1h
q1q1T0_0vT0_0v
pulses witnessed
op 0 at T0_1h: R(1.5708,1.5708)@q0, MS(1.5708)@q0,q1, R(-1.5708,0)@q0, R(-1.5708,0)@q1, R(-1.5708,1.5708)@q0
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (10 instructions, cooled)
#0   init q0@T0_1h, q1@T0_0v
#1   cool all
#2   shuttle q1 T0_0v→T0_1h   ← op 0 cx
#3   gate R q0 @T0_1h   ← op 0 cx
#9   cool all
#4   gate MS q0,q1 @T0_1h   ← op 0 cx
#5   gate R q0 @T0_1h   ← op 0 cx
#6   gate R q1 @T0_1h   ← op 0 cx
#7   gate R q0 @T0_1h   ← op 0 cx
#8   shuttle q1 T0_1h→T0_0v   ← op 0 cx

cz q[0],q[1]; a CNOT with two more pulses around it, on the same pair of ions

device: race8, an eight-site racetrack S0–S7: one loop of trap sites, no junctions

the circuit
q0q1
input
cz q[0],q[1];
ion mapping
qubitionstartsends
q0q0S0S0
q1q1S1S1
pulses witnessed
op 0 at S0: R(1.5708,-1.5708)@q1, VZ(3.14159)@q1, R(1.5708,1.5708)@q0, MS(1.5708)@q0,q1, R(-1.5708,0)@q0, R(-1.5708,0)@q1, R(-1.5708,1.5708)@q0, R(1.5708,-1.5708)@q1, VZ(3.14159)@q1
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
28 rules hold, R7 failR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (13 instructions, cooled)
#0   init q0@S0, q1@S1
#1   cool all
#2   shuttle q1 S1→S0   ← op 0 cz
#3   gate R q1 @S0   ← op 0 cz
#4   gate VZ q1 @S0   ← op 0 cz
#5   gate R q0 @S0   ← op 0 cz
#6   gate MS q0,q1 @S0   ← op 0 cz
#7   gate R q0 @S0   ← op 0 cz
#8   gate R q1 @S0   ← op 0 cz
#9   gate R q0 @S0   ← op 0 cz
#10  gate R q1 @S0   ← op 0 cz
#11  gate VZ q1 @S0   ← op 0 cz
#12  shuttle q1 S0→S1   ← op 0 cz

swap q[0],q[1]; three CNOTs in a row, so three two-ion pulses at one trap

device: ring6d, the six-site ring with two dock spurs

the circuit
q0q1
input
swap q[0],q[1];
ion mapping
qubitionstartsends
q0q0A0A0
q1q1A3A3
pulses witnessed
op 0 at A0: R(1.5708,1.5708)@q0, MS(1.5708)@q0,q1, R(-1.5708,0)@q0, R(-1.5708,0)@q1, R(-1.5708,1.5708)@q0, R(1.5708,1.5708)@q1, MS(1.5708)@q1,q0, R(-1.5708,0)@q1, R(-1.5708,0)@q0, R(-1.5708,1.5708)@q1, R(1.5708,1.5708)@q0, MS(1.5708)@q0,q1, R(-1.5708,0)@q0, R(-1.5708,0)@q1, R(-1.5708,1.5708)@q0
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (26 instructions, cooled)
#0   init q0@A0, q1@A3
#1   cool all
#2   shuttle q1 A3→S4   ← op 0 swap
#3   shuttle q1 S4→S5   ← op 0 swap
#4   shuttle q1 S5→A0   ← op 0 swap
#5   gate R q0 @A0   ← op 0 swap
#23  cool all
#6   gate MS q0,q1 @A0   ← op 0 swap
#7   gate R q0 @A0   ← op 0 swap
#8   gate R q1 @A0   ← op 0 swap
#9   gate R q0 @A0   ← op 0 swap
#10  gate R q1 @A0   ← op 0 swap
#24  cool all
#11  gate MS q1,q0 @A0   ← op 0 swap
#12  gate R q1 @A0   ← op 0 swap
#13  gate R q0 @A0   ← op 0 swap
#14  gate R q1 @A0   ← op 0 swap
#15  gate R q0 @A0   ← op 0 swap
#25  cool all
#16  gate MS q0,q1 @A0   ← op 0 swap
#17  gate R q0 @A0   ← op 0 swap
#18  gate R q1 @A0   ← op 0 swap
#19  gate R q0 @A0   ← op 0 swap
#20  shuttle q1 A0→S5   ← op 0 swap
#21  shuttle q1 S5→S4   ← op 0 swap
#22  shuttle q1 S4→A3   ← op 0 swap

measure q[0] -> c[0]; reading the qubit out, in a trap that can do it: a laser asks the ion whether it is 0 or 1

device: chain4, a four-site linear register C0–C3, every site a trap, no junctions

the circuit
q0q1
input
measure q[0] -> c[0];
ion mapping
qubitionstartsends
q0q0C1C1
q1q1C0C0
pulses witnessed
no pulses: nothing for a tableau to compose, and no witness needed
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (3 instructions, cooled)
#0   init q0@C1, q1@C0
#1   cool all
#2   measure q0   ← op 0 measure

reset q[0]; putting the qubit back to 0, with a laser, in the same kind of trap

device: race8, an eight-site racetrack S0–S7: one loop of trap sites, no junctions

the circuit
q0q1|0⟩
input
reset q[0];
ion mapping
qubitionstartsends
q0q0S0S0
q1q1S1S1
pulses witnessed
no pulses: nothing for a tableau to compose, and no witness needed
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (3 instructions, cooled)
#0   init q0@S0, q1@S1
#1   cool all
#2   reset q0   ← op 0 reset

The algorithm

The pipeline above says what happens to a circuit, and the cards show the result for every basic gate. This section states the problem each pass solves, the algorithm that solves it, and the proposition the checker decides afterwards, for the compiler that produced every programme on this page and the leaderboard entries.

How to read it. Each numbered definition, algorithm, theorem or check is stated once, formally, with a line in words underneath. It is then followed by a green Example, drawn as a diagram, on one of four circuits compiled for this section: circuit 1, two Bell pairs then a joining CNOT, on the 2×3 lattice; circuit 2, a GHZ chain, on the four-site register; circuit 3, a three-qubit parity check, on the six-site ring by rigid rotation; and a Toffoli, for the lowering. The Bell pair of the worked example above is used where two qubits suffice. Every diagram is drawn from the device document and the compiler's own certificate, and the placement traces re-execute the placer's rules and are checked against the layout it chose. The four circuits can be played in §11.

1. Setting and problem statement

Definition 1 device. An expanded architecture is a tuple A = (V, E, cap, gate, spam, L) where V = T ⊔ J is a set of nodes partitioned into traps and junctions, E ⊆ V×V is the set of segments, cap: T → ℕ is the trap capacity, gate, spam ⊆ T are the traps in which a gate or a measurement may happen, and L is a set of named loops, each a cyclic sequence of nodes with a movement class per direction.

In words. The device is a graph. Some nodes are traps, where ions can sit (up to a capacity) and, in some of them, be gated or measured; the other nodes are junctions, where rails cross; the edges are the rails. Some rails form named loops that the control system can turn as a whole. This document is the same one the studio draws, and it is all the compiler ever reads about the hardware.

Example The three devices of this section, with their traps (discs), junctions (squares) and rails. On the lattice every trap can gate and measure and there is no loop. On the ring, the six loop sites S0–S5 (yellow) hold ions but cannot gate; only the two docks A0 and A3 (blue), each on a spur off the loop, can. The register is four traps in a line, no junction at all.
J0_0J0_1J0_2J1_0J1_1J1_2T0_0hT0_1hT0_2hT0_0vT0_1vT1_0vT1_1v
the 2×3 lattice: 7 traps, 6 junctions
S0S1S2S3S4S5A0A3
the six-site ring: loop L0 = S0…S5, docks A0 (on S0) and A3 (on S3)
C0C1C2C3
the four-site register
Definition 2 trap graph. The trap graph GT = (T, H) has an edge, a hop h = (t, t′, via, junc), for every path in (V, E) from trap t to trap t′ whose interior nodes are junctions only, with at most three of them; via(h) is its segment list and junc(h) its junctions. d(t, t′) is the shortest-path distance in GT, and ecc(t) = maxt′ d(t, t′) the eccentricity of a trap.

In words. A hop is what one machine cycle can do to an ion: carry it from a trap to a neighbouring trap, passing through junctions on the way without stopping, because an ion never rests on a junction (R2). The compiler plans on the graph of traps and hops, not on the raw rails. The distance between two traps is the fewest hops between them.

Example The four hops out of the lattice's central trap, each one cycle long. Every one passes through a junction and crosses two rails. Two traps on the same row, such as T0_1h and T0_0h, are two hops apart, and the two ends of the lattice, T0_0h and T0_2h, are 3. T0_1h has eccentricity 2, the smallest, so it is the most central trap; the two row ends have eccentricity 3.
J0_0J0_1J0_2J1_0J1_1J1_2T0_0hT0_1hT0_2hT0_0vT0_1vT1_0vT1_1v
the four hops out of T0_1h: to T0_0v (blue) and T0_1v (green) through J0_1, to T1_0v (orange) and T1_1v (purple) through J1_1
Definition 3 circuit. A circuit is C = (Q, ⟨o0, …, om−1⟩) with n = |Q| qubits and operations in program order, each with a qubit set q(o) ⊆ Q and a wire set (its qubits and classical bits). The dependency DAG has an edge oi → oj whenever the two are consecutive on some wire. The interaction graph W on Q has weight w(a, b) = the number of two-qubit operations on {a, b}.

In words. Two operations must keep their order only if they touch a common qubit (or classical bit); otherwise they are independent. Drawing an arrow from each operation to the next one on each of its wires gives the dependency graph. The interaction graph forgets the order and only counts how many two-qubit gates each pair of qubits shares.

Example Circuit 1 is h q[0]; h q[2]; cx q[0],q[1]; cx q[2],q[3]; cx q[1],q[2]; measure q -> c;. Its dependency graph, laid out so that each column is one layer of §4: an arrow means "must come after". The two Hadamards depend on nothing; the third CNOT waits for both of the first two; each measurement waits for the last gate on its qubit.
layer 0layer 1layer 2layer 3q0q1q2q3o0: h q0o1: h q2o2: cx q0,q1o3: cx q2,q3o4: cx q1,q2o5: measure q0o6: measure q1o7: measure q2o8: measure q3
the dependency graph of circuit 1; orange boxes are two-qubit gates, blue single-qubit gates, grey measurements

Its interaction graph is a path: three pairs, one CNOT each. Circuit 2 has the same interaction graph but a very different dependency graph, a single chain, because every CNOT shares a qubit with the next.

w = 1w = 1w = 1q0weight 1q1weight 2q2weight 2q3weight 1
the interaction graph of circuits 1 and 2
Definition 4 programme and certificate. A programme P is a sequence of instructions, each occupying one machine cycle: transport (a set of moves, or one loop rotation), pulses, cooling, readout. A certificate κ = (μ, init, moves, rots, gates) consists of the qubit-to-ion map μ: Q → I, the initial position init: I → T, the movement events with their cycles, and one witness per gate naming the instruction, the trap and the ions. The replay post: I → T is the position function obtained by applying the events before cycle t to init.

In words. Besides the programme, the compiler hands over a certificate: which ion plays which qubit, where each ion starts, every move it will make and when, and for every gate a claim of the form "this gate happened at this instruction, in this trap, on these ions". Replaying the moves from the start tells you where every ion is at every cycle, and each claim can be checked against that.

Example The Bell pair's certificate is small enough to draw in full. Ion q0 starts at C1 and q1 at C0; the one move carries q0 to C0 in cycle 3. The two witnesses, for the Hadamard at cycle 2 and the CNOT at cycle 8, are the shaded columns: at each, the replay finds the named ions in the named trap, so the columns are green.
the Bell certificate, replayed cycle by cyclet = 0t = 1t = 2t = 3t = 4t = 5t = 6t = 7t = 8t = 9witness: op 0 at C1witness: op 1 at C0q0C1C1C1C1C0C0C0C0C0C0q1C0C0C0C0C0C0C0C0C0C0
where each ion is at the start of every cycle, from the initial placement and the one move; a witness column is green when the ions it names are where it says
Problem compilation. Given (A, C), produce (P, κ) such that (i) P satisfies every rule of the rule set it is given (the standard set unless another is given; see the Rules page) (legality); (ii) κ satisfies Implements(A, C, κ) of §9 (realisation); (iii) the unitary of the pulses of P, read through μ, equals that of C up to global phase (semantics); while keeping the number of ion-hops, and the number of cycles, small.

In words. Produce a programme the machine can run, a certificate that places every gate of the circuit once, in order, in a trap where its ions are together, and pulses that compute the right thing; and make it short. Hops are the cost that matters physically: each hop heats its ion, and a hot ion gates worse (R7, R16), so a programme that moves ions further is not only slower but less accurate.

Conditions (i)–(iii) are decided after the fact by checkers that share no code with the compiler (§9); the objective is pursued heuristically, because its two sub-problems are NP-hard: placement is a quadratic assignment problem and routing is multi-agent path finding under capacity constraints. The pipeline is therefore untrusted heuristics followed by a trusted decision procedure. At a glance:

passproblemalgorithmcostdischarged by
§2 loweringarity ≤ 2rewrite tablelinear§9 (iii), tableau route only
§3 placementQAP on W, dgreedy + spectral, 2-swap descentO(n²|W|) per sweepnone (objective only)
§4 layeringDAG schedulingASAP levels, round emissionlinearR12 by construction, §9 (ii)
§5 site selectionmeeting trapargmin over TO(|T|) per gateR6, R6b, R1
§6 routingMAPF with capacities and waveformsprioritised space-time A*O(|T|·H log) per ionR1–R5, R8, R11, R22
§7 conveyorbipartite contacts on a loopreadiness batching, greedy sweeplinear in contactsas §6, plus R4d
§8 coolingR7 feasibilityreplay and insertone passR7, R7c

2. Lowering

Every operation with |q(o)| ≥ 3 is replaced, before placement, by a sequence of one- and two-qubit operations from a composite table, and the DAG is rebuilt from the rewritten list. All later passes see the lowered circuit C′. The rewrite is checked wherever condition (iii) is checked, because (iii) compares the programme with the original C: by the stabilizer tableau for a Clifford circuit, and for a Toffoli, which is not Clifford, as exact matrices, the Toffoli at its own defining matrix. An incorrect table entry would therefore show as a mismatch.

Example The Toffoli, before and after. The router only ever brings two ions together, so the three-qubit gate on the left becomes the fifteen-gate circuit on the right, which is what the placer and router are given. The six CNOTs meet one pair at a time.
q0q1q2
the source circuit: one Toffoli
q0q1q2HT†TT†TTHTT†
the lowered circuit the compiler works on: 15 operations, read from the certificate

Each of those is then rewritten into pulses (Theorem 1). The tool's own count for the whole Toffoli is 6 two-ion pulses, 33 single-ion pulses and 9 frame updates. Because the T gates are not Clifford, this circuit is checked against the exact 8×8 unitary; its card in §11 says so.

3. Placement

Problem placement. Choose π: Q → Tu with |π−1(t)| ≤ c(t) for every trap, minimising
Φ(π) = ∑{a,b} w(a, b) · d(π(a), π(b)).
Tu ⊆ T is the usable set and c the per-trap start limit, both defined below.

In words. Give every qubit a starting trap so that qubits which will gate together start close together. The score of a layout adds up, over every pair of qubits, "how many gates they share" times "how many hops apart they start". Lower is better. Single-qubit gates do not count: where they happen is decided later, and on a device where every trap gates they cost no transport at all.

Example Circuit 1 on the lattice, with the layout the compiler chose. Each of the three interacting pairs is one hop apart, so the score is 1 + 1 + 1 = 3. It cannot be lower: interacting qubits starting in different traps are at least one hop apart, so the score is at least the number of gates. The right-hand layout is a bad one for comparison: q1 and q2 at the two ends of the lattice, 3 hops apart, so that pair alone costs 3.
J0_0J0_1J0_2J1_0J1_1J1_2T0_0hq3T0_1hq1T0_2hT0_0vq2T0_1vq0T1_0vT1_1vd = 1d = 1d = 1
the compiler's layout: Φ = 3
J0_0J0_1J0_2J1_0J1_1J1_2T0_0hq1T0_1hq0T0_2hq2T0_0vT0_1vT1_0vT1_1vq3d = 3
a poor layout: q1 and q2 far apart, Φ = 1 + 3 + 1 = 5

Usable traps. Let T1 ⊇ T2 ⊇ … be the tiers {gate-capable, non-junction} ⊆ {non-junction} ⊆ {gate-capable} ⊆ T, each restricted to traps of positive capacity. Tu is the first tier whose total capacity ∑ cap(t) is at least n. The start limit is c(t) = 1 if |Tu| ≥ n, otherwise c(t) = cap(t). In words: prefer traps that can gate and are not junctions (a junction holds one ion, and an ion parked on one blocks every route through it for a whole layer); start one ion per trap when there are enough traps, and only pack two into a trap on a device that is tight, which the compiler then reports.

Example On the lattice every trap qualifies: seven traps for four qubits, one ion each. On the ring only the two docks can gate, and together they hold four ions, exactly the four qubits, so the general router would start two ions in each dock and report "device is tight". (Circuit 3 is compiled by the conveyor pass of §7 instead, which lays out riders and docks by its own rule.)
J0_0J0_1J0_2J1_0J1_1J1_2T0_0hT0_1hT0_2hT0_0vT0_1vT1_0vT1_1v
the lattice: all 7 traps usable, one ion each
S0S1S2S3S4S5A0q0 q1A3q2 q3
the ring: only A0 and A3 gate, so two ions per dock
Algorithm 1 greedy weighted insertion.
seed   a₀ ← argmaxa ∑b w(a,b);   π(a₀) ← argmint ∈ Tu ecc(t)   (the most central trap)
repeat n − 1 times
   a ← argmaxa unplaced ∑b placed w(a,b)
   π(a) ← argmint free ∑b placed w(a,b) · d(t, π(b))
A trap is free while it holds fewer than c(t) placed qubits. Ties: the seed is the lowest such qubit, the next qubit the highest-index one among equals, the trap the first in document order. Running time O(n · |Tu| · n).

In words. Start with the busiest qubit in the middle of the device. Then, again and again, take the unplaced qubit with the most gates to qubits already placed, and put it in the free trap closest to its partners.

Example Circuit 1 on the lattice, one step per picture (the newly placed ion is green). q1 and q2 both have two gates; q1 is the lower index, so it is the seed, and it goes to the most central trap. The result is the compiler's layout, score 3.
J0_0J0_1J0_2J1_0J1_1J1_2T0_0hT0_1hq1T0_2hT0_0vT0_1vT1_0vT1_1v
step 1: q1 → T0_1h. the most central trap (eccentricity 2); q1 has the most two-qubit gates (2)
J0_0J0_1J0_2J1_0J1_1J1_2T0_0hT0_1hq1T0_2hT0_0vq2T0_1vT1_0vT1_1v
step 2: q2 → T0_0v. tied to q1; the first free trap at weighted distance 1
J0_0J0_1J0_2J1_0J1_1J1_2T0_0hq3T0_1hq1T0_2hT0_0vq2T0_1vT1_0vT1_1v
step 3: q3 → T0_0h. tied to q2; the first free trap at weighted distance 1
J0_0J0_1J0_2J1_0J1_1J1_2T0_0hq3T0_1hq1T0_2hT0_0vq2T0_1vq0T1_0vT1_1v
step 4: q0 → T0_1v. tied to q1; the first free trap at weighted distance 1

On the register the same rule goes wrong. After q1 is seeded at C1, q2 is placed before q0 (the tie rule prefers the higher index), and it takes C0, the first free trap next to C1. That leaves q0 the trap on the other side, C2, and then q3 has to go three hops from its partner q2. Score 5, exactly the score the compiler reports for its greedy layout. Greedy commits one qubit at a time and never reconsiders; the next two algorithms exist for this case.

C0C1q1C2C3
step 1: q1 → C1. the most central trap (eccentricity 2); q1 has the most two-qubit gates (2)
C0q2C1q1C2C3
step 2: q2 → C0. tied to q1; the first free trap at weighted distance 1
C0q2C1q1C2q3C3
step 3: q3 → C2. tied to q2; the first free trap at weighted distance 2
C0q2C1q1C2q3C3q0
step 4: q0 → C3. tied to q1; the first free trap at weighted distance 2
Algorithm 2 spectral ordering. Let LW = D − W be the Laplacian of the interaction graph and f its Fiedler vector, the eigenvector of the second-smallest eigenvalue, which minimises ∑ w(a,b)(xa − xb)² over unit vectors orthogonal to 𝟙. It is computed by 400 steps of power iteration on dmaxI − LW, re-centred and normalised at each step. Qubits are sorted by f; traps are ordered by breadth-first search of GT from the central trap, each trap repeated c(t) times; the two orders are zipped.

In words. Instead of placing qubits one at a time, spread all of them along a line at once, so that qubits sharing many gates land next to each other (the Fiedler vector is the best such line, in the least-squares sense). Then walk the device outward from its centre, and hand the traps out along that walk, in order.

Example For the path q0 – q1 – q2 – q3 the Fiedler vector puts the four qubits on a line in their own order (up to a sign), so sorting gives q3, q2, q1, q0. On the register the walk from the central trap C1 visits C1, then C0, then C2, then C3, alternating sides. Zipping the two orders gives the layout below: score 4, better than greedy's 5 and the score the compiler reports for it, but not yet 3, because the walk alternates sides of the centre while the line does not.
qubits sorted by the Fiedler vectortraps in breadth-first order from the centreq3 f = -0.66C1q2 f = -0.26C0q1 f = +0.26C2q0 f = +0.66C3
the two orders and their zip: each qubit takes the trap below it
C0q2C1q3C2q1C3q0
the spectral layout on the register: Φ = 2 + 1 + 1 = 4 (q2–q1 are two hops apart)
Algorithm 3 selection and 2-swap descent.
π ← argmin { Φ(πgreedy), Φ(πspectral) }
for at most 40 sweeps, while some swap improved in the last sweep
   for each pair a < b:  if Φ(π ∘ (a b)) < Φ(π) then π ← π ∘ (a b)
return ⟨π, πgreedy, πspectral⟩                (a ranked list)
Φ is blind to routability, so the compiler tries the ranked candidates in turn and keeps the first that routes (§6).

In words. Take whichever of the two layouts scores better, then keep swapping pairs of qubits whenever a swap lowers the score, until no swap does. Keep the other two layouts as spares: a layout can score well and still leave an ion somewhere the router cannot get past later.

Example On the register the spectral layout (score 4) is chosen over greedy (5). The descent tries the six pairs in order; swapping q2 and q3 is the first that helps, taking the score from 4 to 3, and no later swap improves on it, so the descent stops after 2 sweeps. That is the layout the compiler chose, the chain of the circuit laid along the chain of the device; its note reads "hill-climb 4 -> 3 in 2 rounds". On the lattice greedy already scored 3 and no swap improves it.
C0q2C1q3C2q1C3q0
before: the spectral layout, Φ = 4
C0q3C1q2C2q1C3q0
after swapping q2 and q3: Φ = 3, the compiler's layout
the compiler on circuit 1seeded q1 (weight 2) at T0_1h
candidates: greedy 3, spectral 4 -> greedy
weighted interaction distance 3 over 3 distinct pairs
the compiler on circuit 2seeded q1 (weight 2) at C1
candidates: greedy 5, spectral 4 -> spectral
hill-climb 4 -> 3 in 2 rounds
weighted interaction distance 3 over 3 distinct pairs

4. Layering and round emission

Definition 5 ASAP layering. λ(o) = 0 if o has no predecessor in the DAG, otherwise λ(o) = 1 + max{λ(o′) : o′ → o}; equivalently, the length of the longest path from a source to o. The layer Λk = {o : λ(o) = k}.

In words. Every operation goes into the earliest layer it can: one layer after the latest operation it depends on. Layers run one after another; inside a layer, nothing depends on anything else, so everything in it may happen at the same time, as far as the hardware allows.

Example Circuit 1's dependency graph from Definition 3, read column by column: the two Hadamards are layer 0; the two CNOTs, each one arrow later, are layer 1; the third CNOT and the measurements of q0 and q3 are layer 2; the last two measurements are layer 3. Four layers, as the compiler reports. Circuit 2 is one long chain, so each of its five layers holds a single gate (plus the measurements that become ready); there the layering buys nothing and it is the round emission below that still applies.
layer 0layer 1layer 2layer 3q0q1q2q3o0: h q0o1: h q2o2: cx q0,q1o3: cx q2,q3o4: cx q1,q2o5: measure q0o6: measure q1o7: measure q2o8: measure q3
circuit 1 by layer: the columns are the layers

Within a layer, each gate g is decomposed into its pulse sequence pg,1, …, pg,ℓ(g) from the pulse table built on the identities of Theorem 1 (one beam and one frame update for a single-qubit gate; four beams around one two-ion pulse for a CNOT). Pulses are emitted in rounds: round k is the instruction set {pg,k : k ≤ ℓ(g)}, one instruction per pulse kind, all in one machine cycle.

Proposition 1 R12 by construction. If every gate of a layer is assigned a distinct trap (§5), then no round places two gates in one trap, so R12 (one gate per trap per cycle) holds for every emitted cycle. Proof. A round contains at most one pulse per gate, and gates have pairwise distinct traps. ∎ Consequently a layer with r gates costs maxg ℓ(g) pulse cycles rather than ∑g ℓ(g).

In words. Gates in the same layer fire in lock-step: the first pulse of every gate together, then the second pulse of every gate, and so on. Because each gate is in its own trap, this never asks one trap to do two things in a cycle, so a layer of many gates takes as long as one gate.

Example Layer 1 of circuit 1 holds two CNOTs, one at T0_1h and one at T0_0h. Each is five pulses. Read the diagram column by column: every column is one instruction and one machine cycle, carrying the same-numbered pulse of both gates. Instruction #6 is a single two-ion instruction naming two pairs at two traps. Five cycles for two gates.
cx q0,q1 at T0_1hcx q2,q3 at T0_0hinstructionround 0R(π/2, π/2) on q0R(π/2, π/2) on q2#5round 1MS(π/2) on q0, q1MS(π/2) on q2, q3#6round 2R(−π/2, 0) on q0R(−π/2, 0) on q2#7round 3R(−π/2, 0) on q1R(−π/2, 0) on q3#8round 4R(−π/2, π/2) on q0R(−π/2, π/2) on q2#9
round emission for layer 1: columns are cycles, rows are gates; orange is the two-ion pulse

The same happens in layer 0, where the two Hadamards share one beam instruction and one frame instruction (#2, #3), and in layer 2, where the two measurements share one readout instruction (#17), since measurements do not claim traps:

#2   gate R q0,q2 @T0_0v,T0_1v   ← op 0 h, 1 h
#3   gate VZ q0,q2 @T0_0v,T0_1v   ← op 0 h, 1 h
#5   gate R q0,q2 @T0_0h,T0_1h   ← op 2 cx, 3 cx
#6   gate MS q0,q1,q2,q3 @T0_0h,T0_1h   ← op 2 cx, 3 cx
#7   gate R q0,q2 @T0_0h,T0_1h   ← op 2 cx, 3 cx
#8   gate R q1,q3 @T0_0h,T0_1h   ← op 2 cx, 3 cx
#9   gate R q0,q2 @T0_0h,T0_1h   ← op 2 cx, 3 cx
#17  measure q0,q3   ← op 5 measure, 8 measure

Measurements and resets do not claim traps (R12 bounds gates), so a layer emits one readout instruction naming every ion it measures; a barrier orders and costs nothing. The scheme forgoes pipelining across layers: transport for the next layer starts only after the pulses of this one. §10 reports what that costs against an exact solver.

5. Site selection

Let pos be the current positions, K the traps already claimed in this layer, and occ(t) = |pos−1(t)| the number of ions in a trap.

Definition 6 meeting trap. For a two-qubit gate on ions i, j at si, sj,
site(g) = argmin { d(si, t) + d(sj, t) : t ∈ gate ∖ K, room(t) ≥ 2 },
where room(t) = cap(t) − occ(t) + |{si, sj} ∩ {t}|. Ties are broken by document order. A single-qubit gate happens where its ion stands if that trap can gate and is unclaimed, else at the nearest such trap with room; a measurement or reset at the nearest trap that can measure, with no claim. If the set is empty the operation is reported unrealised.

In words. A two-qubit gate happens in the trap that can gate, is not already taken by another gate of this layer, has room for both ions once the ions already parked in it are counted, and is closest to the pair, counting both ions' journeys. Among equals, the first in the document wins.

Example The Bell pair on the register: q0 starts at C1, q1 at C0. Both C0 and C1 are a total of one hop from the pair; C0 comes first in the document, so it is the site, and q0 is the ion that travels. Had the order been the other way round, q1 would have travelled instead: the tie rule is arbitrary but fixed, and the checker does not mind which.
C01 + 0 = 1q1C10 + 1 = 1q0C21 + 2 = 3C32 + 3 = 5
candidates for the Bell CNOT: the number under each trap is d(q0, t) + d(q1, t); C0 is chosen
Example The third CNOT of circuit 1, cx q1,q2, at the start of layer 2. After layer 1, q0 and q1 both stand at T0_1h and q2, q3 at T0_0h; nobody went home, because every ion is used again in layer 2 (Definition 7). The two traps the operands stand in are nearest by distance but are full: two ions each, which is their capacity, and only one of the two is an operand, so they are struck out. Among the rest, the smallest total is two hops, reached by T0_0v and T1_0v; T0_0v comes first in the document. So the pair meets in the trap between them, one hop each.
J0_0J0_1J0_2J1_0J1_1J1_2T0_0h2 hops, fullq2 q3T0_1h2 hops, fullq0 q1T0_2h5 hops, room 2T0_0v2 hops, room 2T0_1v3 hops, room 2T1_0v2 hops, room 2T1_1v3 hops, room 2q1q2
candidates for cx q1,q2: total hops for the two operands and the room left; the full traps are struck out, T0_0v is chosen
#10  shuttle q1 T0_1h→T0_0v   ← op 4 cx
#11  shuttle q2 T0_0h→T0_0v   ← op 4 cx
#12  gate R q1 @T0_0v   ← op 4 cx
#13  gate MS q1,q2 @T0_0v   ← op 4 cx
Definition 7 undocking with one-layer lookahead. After the pulses of Λk, the set Rk = { i : i an operand of a two-qubit gate of Λk, i ∉ ions(Λk+1), pos(i) ≠ init(i) } is routed back to init by the layer router of §6; an ion that cannot be routed home stays and is noted.

In words. When a layer is done, every ion that gated in it and is not needed by the very next layer is sent back to where it started. That keeps the few gate-capable traps of a device free for the gates still to come, and the one-layer lookahead stops the rule from sending an ion home only to fetch it straight back.

Example In circuit 2, the GHZ chain, each layer holds one CNOT and the next layer needs one of its ions: after cx q0,q1 at C2, q1 is wanted by cx q1,q2 and q0 by its measurement, so nobody moves back, and likewise at every layer. The whole circuit costs three hops, one per CNOT. Without the lookahead q1 would have gone back to C2 and set out again.
C0q3C1q2C2q1C3q0q0 (cycle 3)q1 (cycle 9)q2 (cycle 16)
circuit 2: the three moves of the whole programme, one per CNOT; the ions stay where they gated

The swap card above shows the other case: on the ring q1 rides 3 hops to the dock A0, the three CNOTs of the swap fire, and since nothing follows, q1 is returned along the same 3 hops to its starting trap.

S0S1S2S3S4S5A0q0A3q1
the swap: q1 rides to A0 (blue) and, with nothing left to do, home again (grey)

6. Routing within a layer

Problem layer routing. Given pos: I → T, a set of movers M ⊆ I with targets τ: M → T, and a horizon H, find for each i ∈ M a walk in the time-expanded graph GT × {0, …, H} (a hop or a wait per cycle) from (pos(i), 0) to (τ(i), ti) such that, at every cycle, the constraints listed below hold jointly for the movers and the stationary ions I ∖ M; minimise the makespan max ti.

In words. Some ions must get from where they are to the trap their gate was assigned; every other ion stands still and is in the way. Find each mover a route, one hop per cycle with waiting allowed, so that no rule is broken at any cycle, and finish as early as possible. This is multi-agent path finding, with the twist that ions share traps up to a capacity and that, on a broadcast-wired device, everything moving in one cycle must move the same way.

The solver is prioritised planning with a space-time reservation table (cooperative A*): movers are planned one at a time in a priority order; each plan is found by A* over states (t, τ) with actions wait and hop, cost 1 per cycle and the admissible heuristic h(t) = d(t, goal); a finished plan reserves what it uses, and later movers plan around it. A hop h departing t at cycle τ is admissible iff all of the following hold, each of which is one rule of the Rules page:

occ(t′, τ+1) < cap(t′)                                  R1   the destination has room
∀ j ∈ junc(h):  transits(j, τ) < 1                     R2   one transit per junction per cycle
∀ e ∈ via(h):   load(e, τ) < cap(e)                  R3   segment capacity
(t′, t, τ) not reserved                                   R5   no head-on exchange on a segment
one action per ion per cycle                                 R8
act(h) = (ℓ, δ) ⇒ act(ℓ, τ) ∈ {⊥, δ}                          R4d, R11   one signed direction per loop per cycle
wave(τ) ∈ {⊥, sig(h)}      (broadcast devices only)         R22  one waveform per cycle

The waveform signature sig(h) is the movement class followed by one label per segment crossed: along a named loop the signed unit step on that loop; across a spur, inward or outward; otherwise the direction of the lab-frame displacement. It is computed by the same function the verifier uses for R22, so the two agree by construction. The first mover to reserve a cycle fixes its waveform; any other mover whose hop has a different signature waits. Arrival is not sufficient: an ion parks at its goal for the rest of the layer, so the goal must have room at every later cycle too.

Example Layer 1 of circuit 1 on the space-time grid: rows are traps, columns are cycle boundaries, and each arrow is one hop. q0 and q2 must move (blue, orange); q1 and q3 stand still at the two goals (grey). Both movers descend a column and then turn right, the same waveform, so both hops fit in cycle 0 as one instruction (#4). The makespan, 1, equals the lower bound (the longest single distance), so no other priority order is even tried.
T0_1vT0_1hT0_0vT0_0hstart of cycle 0start of cycle 1cycle 0: waveform -y,+xq0q0q2q2q1q1q3q3
layer 1: two hops with the same waveform share cycle 0

Layer 2 is the instructive case. q1 and q2 both head for T0_0v, both one hop away, and the trap has room for both. But q1 turns left then down, and q2 turns left then up: two different waveforms. q1 is planned first and fixes the waveform of cycle 0, so q2 waits a cycle and hops in cycle 1. Every priority order gives two cycles here, so all four are tried and the first is kept, instructions #10 and #11. Nothing physical prevents the two hops sharing a cycle; the cost is R22, one waveform per cycle on a broadcast-wired machine.

T0_1hT0_0hT0_0vstart of cycle 0start of cycle 1start of cycle 2cycle 0: waveform -x,-ycycle 1: waveform -x,+ywaitsq1q1q1waitsq2q2q2q0q0q0q3q3q3
layer 2: different waveforms, so q2 waits one cycle
#4   shuttle q0 T0_1v→T0_1h, q2 T0_0v→T0_0h   ← op 2 cx, 3 cx
#10  shuttle q1 T0_1h→T0_0v   ← op 4 cx
#11  shuttle q2 T0_0h→T0_0v   ← op 4 cx
Algorithm 4 layer routing.
LB ← maxi ∈ M d(pos(i), τ(i));   H ← 2·ecc(GT) + 8
for rung in ⟨(uniform, strict), (¬uniform, strict), (¬uniform, tolerant)⟩
   for H′ in ⟨H, 2H⟩            (the third rung tries H only)
      best ← ⊥
      for order in ⟨farthest first, nearest first, program order, its reverse⟩
         reserve every stationary ion at its trap for cycles 0..H′
         for i in order:  plan i by A*; if none, next order;  reserve its walk and its parking
         lay the hops out by departure cycle;  if ¬uniform, split each cycle by signature
         replay the emitted cycles against R1;  if strict and a trap overflows, next order
         if |cycles| < |best| then best ← cycles;   if |best| ≤ LB then return best
      if best ≠ ⊥ then return best
raise Unroutable
Rungs 1 and 2 guarantee R1 on what is emitted; rung 3 exists so that a layer no arrangement can make both uniform and legal still yields a programme, for the verifier to report.

In words. Try four different orders of planning the movers and keep the plan with the fewest cycles, stopping early if a plan is provably as short as possible. If nothing routes within the search horizon, double it once. If the strict one-waveform search fails, relax it in two steps. Before anything is emitted, replay it and refuse a plan that would overfill a trap.

Example (a small loop) Why the order matters, on a loop of eight slots. Ion a must go from slot 0 to slot 3 and ion b from slot 2 to slot 1. Left: a is planned first, walks 0→1→2→3 and parks at 3; b waits two cycles for a to pass and steps to 1. Makespan 3, which equals the lower bound, so the search stops there. Right: b is planned first, steps to slot 1 at once and parks there for the whole layer; a now finds slot 1 blocked at every cycle and must go the long way round. Makespan 5. No single order avoids this kind of trap on every layer, which is why four are compared. On a racetrack the exact solver of §10 once found a layer where the single order then in use cost 43 cycles against 5.
a planned first01234567abb waits two cycles, then steps 2→1: makespan 3b planned first01234567baslot 1 is taken for good: a goes round, makespan 5
the same two movers on an eight-slot loop, planned in the two orders

Failure is a result. When Algorithm 4 raises, or §5 leaves an operation unrealised, the compiler tries again with the next placement of Algorithm 3; when all three fail on a device with a closed loop and docks, §7 is tried; otherwise the compiler declines with the reason. No branch emits a programme that violates a rule it knows about.

7. The conveyor pass

Definition 8 conveyor device. A closed loop ℓ ∈ L with rail slots r0, …, rN−1 and a set of docks D, each a gate-capable trap joined to one rail slot by one spur segment. A rider i has a fixed slot σ(i) ∈ ℤN and the loop an offset θ ∈ ℤN; the rider stands at rσ(i)+θ. A rotation by δ is one instruction that sets θ ← θ + δ, costing |δ| hops per rider.

In words. Think of the loop as a conveyor belt with a few workstations (the docks) beside it. Ions riding the belt keep their places on it; one instruction advances the whole belt by any number of slots, and it needs no empty slot to do so, because everything moves together.

Example The six-site ring is a conveyor with a belt of six slots and two docks. Circuit 3 has one ancilla, q0, and three data qubits. The pass parks q0 at dock A0 and spreads the three riders two slots apart. Each turn of the belt by two slots, backwards, brings the next rider in the circuit's order to S0, beside the dock: q2, then q3.
S0q1S1S2q2S3S4q3S5A0q0A3
start: q1 is beside the dock
S0q2S1S2q3S3S4q1S5A0q0A3
after rotating by −2: q2 is beside the dock
S0q3S1S2q1S3S4q2S5A0q0A3
after another −2: q3 is beside the dock
Proposition 2 domain of rigid rotation. Rotation preserves the cyclic order of the riders, so two riders never share a trap. Hence a circuit is compilable by rotation alone only if its interaction graph W is bipartite, Q = QD ⊔ QL, with |QD| ≤ |D| parked at docks and |QL| ≤ N riding. The pass two-colours W and refuses, naming a conflicting pair, otherwise.

In words. Two ions on the belt can never meet, so every gate must pair a rider with a docked ion. That works exactly when the qubits split into two groups with all gates running between the groups, one group small enough for the docks: the shape of a syndrome-extraction round, ancillas docked and data riding. It is also why the general router's limit, about half occupancy on a loop, does not apply here.

Example Circuit 3's interaction graph is a star: q0 in the middle, three gates out to q1, q2, q3. Two colours suffice, with q0 alone on the dock side (one ancilla, two docks available) and the three data qubits riding (three riders, six slots). Circuit 2 is bipartite too, but the pass refuses it on this ring for another reason: it measures every qubit, and a rider can never be measured, since only the docks can. The compiler's message when it tried was "measure acts on q1, which rides the loop; only docked ions can gate". A triangle of CNOTs, cx a,b; cx b,c; cx c,a, fails the first condition: whichever two ride the belt can never meet, and the pass says which.
w = 1w = 1w = 1q0weight 3q1weight 1q2weight 1q3weight 1
the interaction graph of circuit 3: a star, with q0 the ancilla on every gate

Layout. Docks are assigned to QD in order and riders spread at stride ⌊N/|QL|⌋, unless a layout is supplied from outside, as the code-aware leaderboard entries do; a supplied layout is validated (each dock exists, no slot or dock named twice, the partition respected) and otherwise treated as data.

Schedule. Operations are emitted by readiness: o is ready when every earlier o′ sharing a qubit with it is emitted, commuting or not. In words: every qubit sees its own operations in the circuit's order, and only operations on different qubits move relative to each other, which is what lets contacts of different ancillas share one batch. The order of a qubit's gates is the circuit author's to choose, so the compiler keeps it even where two CNOTs commute: one that shares only its control, or only its target, with another would give the same unitary in either order, which is exactly why no semantic check could tell, and why the order conjunct of §9 has no exemption for it.

Algorithm 5 greedy sweep.
while operations remain
   drain: emit every ready measurement, reset and single-qubit gate on a docked ion   (no rotation needed)
   for each ready contact c = (rider i, dock Dc):  θc ← rail(Dc) − σ(i)  (mod N)
   θ* ← the θc with the largest batch (ties: nearest, either way)      [monotone variant: nearest ahead]
   B ← a set of ready contacts at θ*, at most one per dock and one per rider
   emit rotate(θ* − θ, the shorter way);  dock(B);  the CNOT rounds of B together;  undock(B)
Invariant: the loop never turns while a dock is occupied. In the certificate a rotation is one event, and the checker's replay applies it to every ion on the loop and to no other.

In words. First do everything that needs no turn: measure, reset and single-qubit gates on docked ions. Then work out, for each gate that is ready, how far the belt would have to turn to bring its rider beside its dock, turn to the position where the most ready gates line up (the nearest, either way, when it is a tie), and do every ready gate there: pull the riders into their docks, fire, push them back out. The belt never turns while a rider is docked, since a docked ion is off the belt and would come back beside the wrong slot. Since every qubit's gates stay in the circuit's order, an ancilla has one gate ready at a time, and turning the shorter way to it costs fewer turns and fewer hops than always turning forward, which would lap the belt for each one; the forward-only rule is still there as an option.

Example Circuit 3, traced. The dock hangs on slot 0, so a rider at slot s needs a turn of −s: q1 needs no turn, q2 (at slot 2) needs −2 (or +4 the long way), q3 (at slot 4) −4 (or +2). The three CNOTs share q0, so they become ready one at a time, in the circuit's order, although they commute. The sweep serves q1 without turning, then cx q0,q2 with a turn of −2; that turn carries q3 from slot 4 to slot 2, so cx q0,q3 needs −2 more: two turns of two, four hops in all, three contacts, exactly as the compiler's note reads. Taking cx q0,q3 first is not an option: the order of q0's gates is the circuit's.
stepreadyturnemitted
drainh q0 (q0 is docked)—beam and frame update, #2–#3
1cx q0,q1none: q1 is already beside the dockdock q1, five rounds, undock: #4–#10
2cx q0,q2 (needs −2)−2rotate (#11), dock q2, rounds, undock: #12–#18
3cx q0,q3 (now needs −2)−2 morerotate (#19), dock q3, rounds, undock: #20–#26
drainh q0, measure q0—#27–#29
#4   dock q1 S0→A0   ← op 1 cx
#6   gate MS q0,q1 @A0   ← op 1 cx
#10  undock q1 A0→S0   ← op 1 cx
#11  rotate_ccw rotate L0 by -2   ← op 2 cx
#12  dock q2 S0→A0   ← op 2 cx
#14  gate MS q0,q2 @A0   ← op 2 cx
#18  undock q2 A0→S0   ← op 2 cx
#19  rotate_ccw rotate L0 by -2   ← op 3 cx
#20  dock q3 S0→A0   ← op 3 cx
#22  gate MS q0,q3 @A0   ← op 3 cx
#26  undock q3 A0→S0   ← op 3 cx

8. Cooling insertion

Let n̄i(t) be the motional quanta of ion i at cycle t under the heating model (each hop, split and merge adds a table value; a global cool sets every n̄i to zero). R7 requires, for every two-qubit gate g at cycle t, maxi ∈ g n̄i(t) ≤ budget. The pass replays P, inserts a global cool immediately before each violating gate, and replays once more.

Proposition 3 one pass suffices. After a single pass no gate violates R7. Proof sketch. Inserting a cool before cycle t sets every n̄i(t) to zero and, heating being additive and non-negative, does not increase n̄i(t′) for any t′ > t; hence a gate that satisfied R7 before still does, and a gate that violated it now starts from zero. ∎

In words. Moving an ion warms it up, and a warm ion makes a worse two-qubit gate. The pass walks through the programme with a thermometer, and wherever a two-qubit gate would fire too hot it inserts a cooling step just before it. Cooling is global, so one step cools every ion; that is why one walk is enough, and the pass checks the result by walking through again.

Example Circuit 1 leaves the compiler with 19 instructions and the cooling pass returns 21. The strip below is the cooled programme in order: the two red-bordered boxes are the cooling steps the pass inserted, each immediately before a two-ion pulse (instructions #6 and #13), whose operands the replay had found above the budget after their hops. The first cooling step, at #1, is state preparation and is always there. The pulses and moves are untouched, so the certificate still applies: a cool moves nothing.
init#0cool#1R#2VZ#3move#4R#5cool#19R7MS#6R#7R#8R#9move#10move#11R#12cool#20R7MS#13R#14R#15R#16meas#17meas#18
the cooled programme of circuit 1: orange boxes are two-ion pulses, blue beams, green moves; the cools marked R7 were inserted by the pass

9. Correctness

The compiler is outside the trusted base. Conditions (i)–(iii) of the Problem are decided by three independent checkers, each reading only (A, C, P, κ). The checker for (ii) is proved correct (Theorem 2); the checkers for (i) and (iii) are executable and not proved (Checks 1 and 2). The gate rewrite rests on proved identities.

Theorem 1 pulse identities, proved.
u3(θ, φ, λ) = VZ(φ + λ) · R(θ, π/2 − λ),
CX = e−iπ/4 (Ry(−π/2) ⊗ I)(Rx(−π/2) ⊗ Rx(−π/2)) MS(π/2) (Ry(π/2) ⊗ I),
where R(θ, φ) is a resonant single-ion pulse, VZ a frame update (no laser, no duration) and MS(θ) the two-ion Mølmer–Sørensen interaction. Every supported gate is a u3 and every composite reduces to these two.

In words. Any single-qubit gate is one laser pulse plus a bookkeeping change of phase that costs nothing; a CNOT is one two-ion pulse with four single-ion pulses around it. Both facts are theorems, checked by a proof assistant, and the table is also tested numerically. The global phase is kept because it becomes visible once the gate is controlled, and a wrong phase convention is exactly the kind of error that hides until then.

Example The Bell pair's Hadamard is u3(π/2, 0, π), which becomes one pulse and one frame update; its witness lists them in that order. The frame update costs no cycle, but it is not nothing: a compiler that dropped it as free would emit the pulse alone, which is not a Hadamard. The CNOT's five pulses are the second identity read from right to left.
h q0: 1 pulse + 1 frame updatecx q0,q1: 5 pulsespulse1stR(π/2, −π/2) on q0R(π/2, π/2) on q02ndVZ(π) on q0MS(π/2) on q0, q13rdR(−π/2, 0) on q04thR(−π/2, 0) on q15thR(−π/2, π/2) on q0
the Bell pair's two gates as pulse sequences, read from their witnesses: blue is a single-ion pulse, grey a frame update, orange the two-ion pulse
Check 1 legality. The verifier of the Rules page, which shares no code with the router, replays the cooled programme from its starting positions and decides every rule of the rule set.

In words. The same rule checker the studio runs on any hand-written programme is run on the compiled one, and it does not know or care how the programme was made. A router bug shows up as a failed rule on this page, not as a programme a machine would refuse.

Example For circuit 1 the verifier reports 25 rules passed and none failed (the badge on its card in §11). Suppose the router had let q1 and q2 hop in the same cycle of layer 2, which §6 showed it must not: the replay would find two waveforms in one transport instruction and report R22 failed, with the instruction number, here on this page.
Definition 9 Implements. For a certificate κ over (A, C), with hops HA, gate-capable traps gateA and loop orders loopsA extracted from A, and post the replay of Definition 4, Implements is the conjunction of:
  1. unrealised(κ) = ∅;
  2. μ is injective and total on Q;
  3. the events are sorted by cycle, so the replay is well defined;
  4. every rotation names a loop in loopsA;
  5. ∀ m ∈ moves: (m.src, m.dst) ∈ HA and posm.t(m.ion) = m.src;
  6. ∀ g ∈ gates: g.site ∈ gateA and ∀ i ∈ g.ions: posg.t(i) = g.site;
  7. ∀ g ∈ gates: the ions g names are, in some order, μ of the qubits of the operation it names;
  8. every operation of C′ other than measure, reset and barrier has exactly one witness;
  9. every witness names an operation of C′;
  10. for operations o before o′ sharing a qubit, the witness cycle of o precedes that of o′, whether or not the two commute.

In words. Nothing was left out; each qubit has its own ion; the moves can be replayed in order; every rotation is of a real loop; no ion ever teleports (every move is a real hop, starting from where the ion actually is); every claim names exactly the ions its operation's qubits live on, and finds them together in a trap that can gate; every gate of the circuit is claimed exactly once, and every claim names an operation of the circuit; and gates on a common qubit happen in the order written. A claim names an operation, never the gate applied there, so a claim on a barrier, a measurement or a reset passes too, and which gate fires is for Check 2 to decide.

Example The Bell certificate from Definition 4, replayed twice. Left, as the compiler wrote it: both witness columns are green, because at cycle 2 q0 is at C1 where the Hadamard is claimed, and at cycle 8 both ions are at C0 where the CNOT is claimed. Right, one number changed: the move delayed from cycle 3 to cycle 9. Now at cycle 8 the replay still has q0 at C1, the CNOT's witness is false, and conjunct (6) fails. Deleting the Hadamard's witness would fail (8), an operation with no witness; sending the move to C3 instead of C0 would fail (5), since C1–C3 is not a hop. Each is one of the fourteen mutations of Theorem 2, and each is rejected.
as compiled: the move at cycle 3t = 0t = 1t = 2t = 3t = 4t = 5t = 6t = 7t = 8t = 9witness: op 0 at C1witness: op 1 at C0q0C1C1C1C1C0C0C0C0C0C0q1C0C0C0C0C0C0C0C0C0C0
accepted
mutated: the move at cycle 9t = 0t = 1t = 2t = 3t = 4t = 5t = 6t = 7t = 8t = 9witness: op 0 at C1witness: op 1 at C0 ✗q0C1C1C1C1C1C1C1C1C1C1q1C0C0C0C0C0C0C0C0C0C0
rejected: at cycle 8 the ions are not together
Theorem 2 soundness of the checker. The checker is defined as check(κ) := decide(Implements(κ)), and the theorem check(κ) = true → Implements(κ) has a machine-checked proof that assumes nothing beyond propositional extensionality. The extraction of HA, gateA and loopsA from A is performed by code the compiler never executes. Fourteen mutations of real certificates (dropped, duplicated and shifted witnesses, a teleported move, a wrong departure, an ungateable site, aliased qubits, an operation marked unrealised, unsorted events, reordered and swapped dependent gates, two swapped CNOTs that commute, a witness naming other ions than its operation's, swapped operands) are rejected in practice: thirteen by this checker, and the fourteenth, swapped operands, which moves no ion and names the same two ions, by Check 2.

In words. The checker is nothing but a decision procedure for Definition 9, and a machine-checked proof says that whenever it answers yes, the definition really holds. So the whole claim lives in the definition, which a reader can judge. The facts about the device that the definition refers to (which traps gate, which pairs are one hop apart, how each loop is ordered) are read out of the document by code the compiler never runs, so the compiler cannot make the device bigger by saying so; that is what makes the guarantee hold for any device.

Example What "any device" buys. Suppose a compiler, by a bug, believed the loop site S2 of the ring could gate, and emitted a contact there; its witness would name S2, the checker's list of gate-capable traps is {A0, A3}, and conjunct (6) fails. Suppose instead it believed S0 and S3 were adjacent and moved an ion across in one cycle: that pair is not a hop of the ring, and (5) fails. The compiler cannot argue with either, because nothing it writes is consulted for the device facts.
S0S1S2S3S4S5A0A3not a hop
two things a wrong compiler might claim on the ring, both refused: a gate at S2 (not a gate trap), a hop S0→S3 (not adjacent)
Check 2 semantics. Let U(P) be the unitary of the pulses of P, read out of the emitted programme and composed through μ, and U(C) that of the source circuit. For a Clifford C the checker compares stabilizer tableaux, T(U(P)) = T(U(C)); otherwise, for n ≤ 10 (one more qubit for each measurement or reset in the middle of the circuit), it compares U(P) with U(C), the matrix of the source circuit, each gate at its defining matrix, up to global phase; for a larger circuit outside the Clifford gates, (iii) is reported as not checked. The comparison is executable; it is not proved.

In words. Finally, does the programme compute the right thing? The checker reads the pulses back out of the programme and works out what they do to the qubits, then compares with what the circuit does. For Clifford circuits this is done with stabilizer tableaux, which scale; otherwise the full matrix is compared, up to ten qubits. A wrong angle, a dropped frame update, a swapped control and target, or one gate compiled as another all change the answer. It is the only check that sees which gate the pulses make.

Example The Bell circuit turns the two generators of |00⟩ into X⊗X and Z⊗Z, top row. The checker rebuilds the same map from the seven emitted pulses and finds it equal; the card says "O2: ok". Two wrong programmes, in red: with control and target exchanged, the second generator stays I⊗Z; with the Hadamard's frame update dropped, the pulse alone sends Z to −X and the first generator comes out as −X⊗X, only a sign, but a different tableau and a different Bell state. Circuits 1, 2 and 3 are all Clifford and are checked this way; the Toffoli is not, and its card says the exact unitary was compared.
start |00⟩Z ⊗ II ⊗ Zafter H on q0X ⊗ II ⊗ Zafter CX(q0→q1)X ⊗ XZ ⊗ ZCX reversed (q1→q0)X ⊗ II ⊗ Zframe update dropped−X ⊗ XZ ⊗ Z
the stabilizer generators through the Bell circuit, and the two mutations

Together: Check 1 gives (i), Theorem 2 gives (ii), Check 2 gives (iii), and Theorem 1 is why the compiler's pulse table can be right in the first place; that the pulses of P are the gates of C is what Check 2 establishes. The page's drawing is derived from the same certificate: the studio joins the programme to the circuit through the per-instruction stamps and refuses to draw if a witness disagrees with the stamp on the instruction it names.

10. Limitations and measured gaps

Optimality. Nothing above certifies minimality. The router's layer instances were re-solved exactly by a SAT encoding of the same problem on the same trap graph; the heuristic was optimal on every instance of the lattice and cyclone devices and lost on a racetrack, where a single priority order had cost 43 cycles against 5, which is the origin of the four orders in Algorithm 4. The placement relaxation of Algorithm 2 was predicted to dominate Algorithm 1 and did not; the 2-swap descent on Φ is what won, by up to 12 %.

Scope. Routing is planned within a layer; cross-layer pipelining is not attempted. R10 is reported partial for a non-Clifford circuit of more than ten qubits, where neither a tableau nor a dense unitary is available. Operations on three or more qubits are lowered, never executed as such. The general router runs out at about 46 % loop occupancy, and the conveyor pass covers only bipartite circuits. Whether the source circuit is the intended one (for a syndrome round, whether it measures the intended stabilizers) is outside R10 and is tested upstream. The physical model behind R7 and R16 is the subject of the Physics page.

Example Circuit 1 shows the pipelining limit. At the end of layer 1, q1 and q2 are already known to be heading for T0_0v, and q2 could have set off while the last three beams of layer 1 fired on q0 and q1; instead the layer's transport begins after its last pulse. A cross-layer scheduler could overlap two cycles here, and proportionally more on a long chain. The checker would accept such a programme just as it accepts this one; what stops it is the compiler's structure, not the rules.

Background.

11. The four circuits, compiled and verified

The examples quoted above, through the same pipeline and the same checks as every gate: the input, the programme it became, the ion mapping, the pulses witnessed, and the verdicts. Press Play, or step the machine.

Circuit 1: two Bell pairs, then joined four layers: two Hadamards fire in one instruction, two CNOTs run side by side in two traps, then one CNOT joins the pairs

device: grid2x3, a 2×3 lattice: T-junctions and corners, one trap on every wire

the circuit
q0q1q2q3HH
input
h q[0];
h q[2];
cx q[0],q[1];
cx q[2],q[3];
cx q[1],q[2];
measure q -> c;
ion mapping
qubitionstartsends
q0q0T0_1vT0_1h
q1q1T0_1hT0_0v
q2q2T0_0vT0_0v
q3q3T0_0hT0_0h
pulses witnessed
op 0 at T0_1v: R(1.5708,-1.5708)@q0, VZ(3.14159)@q0op 1 at T0_0v: R(1.5708,-1.5708)@q2, VZ(3.14159)@q2op 2 at T0_1h: R(1.5708,1.5708)@q0, MS(1.5708)@q0,q1, R(-1.5708,0)@q0, R(-1.5708,0)@q1, R(-1.5708,1.5708)@q0op 3 at T0_0h: R(1.5708,1.5708)@q2, MS(1.5708)@q2,q3, R(-1.5708,0)@q2, R(-1.5708,0)@q3, R(-1.5708,1.5708)@q2op 4 at T0_0v: R(1.5708,1.5708)@q1, MS(1.5708)@q1,q2, R(-1.5708,0)@q1, R(-1.5708,0)@q2, R(-1.5708,1.5708)@q1
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (21 instructions, cooled)
#0   init q0@T0_1v, q1@T0_1h, q2@T0_0v, q3@T0_0h
#1   cool all
#2   gate R q0,q2 @T0_0v,T0_1v   ← op 0 h, 1 h
#3   gate VZ q0,q2 @T0_0v,T0_1v   ← op 0 h, 1 h
#4   shuttle q0 T0_1v→T0_1h, q2 T0_0v→T0_0h   ← op 2 cx, 3 cx
#5   gate R q0,q2 @T0_0h,T0_1h   ← op 2 cx, 3 cx
#19  cool all
#6   gate MS q0,q1,q2,q3 @T0_0h,T0_1h   ← op 2 cx, 3 cx
#7   gate R q0,q2 @T0_0h,T0_1h   ← op 2 cx, 3 cx
#8   gate R q1,q3 @T0_0h,T0_1h   ← op 2 cx, 3 cx
#9   gate R q0,q2 @T0_0h,T0_1h   ← op 2 cx, 3 cx
#10  shuttle q1 T0_1h→T0_0v   ← op 4 cx
#11  shuttle q2 T0_0h→T0_0v   ← op 4 cx
#12  gate R q1 @T0_0v   ← op 4 cx
#20  cool all
#13  gate MS q1,q2 @T0_0v   ← op 4 cx
#14  gate R q1 @T0_0v   ← op 4 cx
#15  gate R q2 @T0_0v   ← op 4 cx
#16  gate R q1 @T0_0v   ← op 4 cx
#17  measure q0,q3   ← op 5 measure, 8 measure
#18  measure q1,q2   ← op 6 measure, 7 measure

Circuit 2: a GHZ chain every CNOT shares a qubit with the next: the placer lays the chain along the register, and no ion is sent home while the next gate still needs it

device: chain4, a four-site linear register C0–C3, every site a trap, no junctions

the circuit
q0q1q2q3H
input
h q[0];
cx q[0],q[1];
cx q[1],q[2];
cx q[2],q[3];
measure q -> c;
ion mapping
qubitionstartsends
q0q0C3C2
q1q1C2C1
q2q2C1C0
q3q3C0C0
pulses witnessed
op 0 at C3: R(1.5708,-1.5708)@q0, VZ(3.14159)@q0op 1 at C2: R(1.5708,1.5708)@q0, MS(1.5708)@q0,q1, R(-1.5708,0)@q0, R(-1.5708,0)@q1, R(-1.5708,1.5708)@q0op 2 at C1: R(1.5708,1.5708)@q1, MS(1.5708)@q1,q2, R(-1.5708,0)@q1, R(-1.5708,0)@q2, R(-1.5708,1.5708)@q1op 3 at C0: R(1.5708,1.5708)@q2, MS(1.5708)@q2,q3, R(-1.5708,0)@q2, R(-1.5708,0)@q3, R(-1.5708,1.5708)@q2
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
28 rules hold, R7 failR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (25 instructions, cooled)
#0   init q0@C3, q1@C2, q2@C1, q3@C0
#1   cool all
#2   gate R q0 @C3   ← op 0 h
#3   gate VZ q0 @C3   ← op 0 h
#4   shuttle q0 C3→C2   ← op 1 cx
#5   gate R q0 @C2   ← op 1 cx
#6   gate MS q0,q1 @C2   ← op 1 cx
#7   gate R q0 @C2   ← op 1 cx
#8   gate R q1 @C2   ← op 1 cx
#9   gate R q0 @C2   ← op 1 cx
#10  shuttle q1 C2→C1   ← op 2 cx
#11  gate R q1 @C1   ← op 2 cx
#12  gate MS q1,q2 @C1   ← op 2 cx
#13  gate R q1 @C1   ← op 2 cx
#14  gate R q2 @C1   ← op 2 cx
#15  gate R q1 @C1   ← op 2 cx
#16  measure q0   ← op 4 measure
#17  shuttle q2 C1→C0   ← op 3 cx
#18  gate R q2 @C0   ← op 3 cx
#19  gate MS q2,q3 @C0   ← op 3 cx
#20  gate R q2 @C0   ← op 3 cx
#21  gate R q3 @C0   ← op 3 cx
#22  gate R q2 @C0   ← op 3 cx
#23  measure q1   ← op 5 measure
#24  measure q2,q3   ← op 6 measure, 7 measure

Circuit 3: a parity check, by rotation the ancilla q0 sits at a dock, the data ride the loop; the loop turns twice and every CNOT is a contact at the dock

device: ring6d, the six-site ring with two dock spurs

the circuit
q0q1q2q3HH
input
h q[0];
cx q[0],q[1];
cx q[0],q[2];
cx q[0],q[3];
h q[0];
measure q[0] -> c[0];
ion mapping
qubitionstartsends
q0q0A0A0
q1q1S0S0
q2q2S2S0
q3q3S4S0
pulses witnessed
op 0 at A0: witnessed by instruction #3, pulses in the programmeop 1 at A0: witnessed by instruction #9, pulses in the programmeop 2 at A0: witnessed by instruction #17, pulses in the programmeop 3 at A0: witnessed by instruction #25, pulses in the programmeop 4 at A0: witnessed by instruction #28, pulses in the programme
verdict · stabilizer tableau, composed from the emitted pulses, against the circuit as written
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (33 instructions, cooled)
#0   init q0@A0, q1@S0, q2@S2, q3@S4
#1   cool all
#2   gate R q0 @   ← op 0 h
#3   gate VZ q0 @   ← op 0 h
#4   dock q1 S0→A0   ← op 1 cx
#5   gate R q0 @A0   ← op 1 cx
#30  cool all
#6   gate MS q0,q1 @A0   ← op 1 cx
#7   gate R q0 @A0   ← op 1 cx
#8   gate R q1 @A0   ← op 1 cx
#9   gate R q0 @A0   ← op 1 cx
#10  undock q1 A0→S0   ← op 1 cx
#11  rotate_ccw rotate L0 by -2   ← op 2 cx
#12  dock q2 S0→A0   ← op 2 cx
#13  gate R q0 @A0   ← op 2 cx
#31  cool all
#14  gate MS q0,q2 @A0   ← op 2 cx
#15  gate R q0 @A0   ← op 2 cx
#16  gate R q2 @A0   ← op 2 cx
#17  gate R q0 @A0   ← op 2 cx
#18  undock q2 A0→S0   ← op 2 cx
#19  rotate_ccw rotate L0 by -2   ← op 3 cx
#20  dock q3 S0→A0   ← op 3 cx
#21  gate R q0 @A0   ← op 3 cx
#32  cool all
#22  gate MS q0,q3 @A0   ← op 3 cx
#23  gate R q0 @A0   ← op 3 cx
#24  gate R q3 @A0   ← op 3 cx
#25  gate R q0 @A0   ← op 3 cx
#26  undock q3 A0→S0   ← op 3 cx
#27  gate R q0 @   ← op 4 h
#28  gate VZ q0 @   ← op 4 h
#29  measure q0   ← op 5 measure

A Toffoli, lowered one three-qubit gate becomes six CNOTs and nine single-qubit gates before placement; R10 is decided against the exact unitary

device: grid2x3, a 2×3 lattice: T-junctions and corners, one trap on every wire

the circuit
q0q1q2HT†TT†TTHTT†
input
ccx q[0],q[1],q[2];
ion mapping
qubitionstartsends
q0q0T0_1hT0_1h
q1q1T0_1vT0_1v
q2q2T0_0vT0_1v
pulses witnessed
op 0 at T0_0v: R(1.5708,-1.5708)@q2, VZ(3.14159)@q2op 1 at T0_0v: R(1.5708,1.5708)@q1, MS(1.5708)@q1,q2, R(-1.5708,0)@q1, R(-1.5708,0)@q2, R(-1.5708,1.5708)@q1op 2 at T0_0v: R(0,2.35619)@q2, VZ(-0.785398)@q2op 3 at T0_1h: R(1.5708,1.5708)@q0, MS(1.5708)@q0,q2, R(-1.5708,0)@q0, R(-1.5708,0)@q2, R(-1.5708,1.5708)@q0op 4 at T0_1h: R(0,0.785398)@q2, VZ(0.785398)@q2op 5 at T0_1v: R(1.5708,1.5708)@q1, MS(1.5708)@q1,q2, R(-1.5708,0)@q1, R(-1.5708,0)@q2, R(-1.5708,1.5708)@q1op 6 at T0_1v: R(0,2.35619)@q2, VZ(-0.785398)@q2op 8 at T0_1h: R(0,0.785398)@q1, VZ(0.785398)@q1op 7 at T0_1v: R(1.5708,1.5708)@q0, MS(1.5708)@q0,q2, R(-1.5708,0)@q0, R(-1.5708,0)@q2, R(-1.5708,1.5708)@q0op 9 at T0_1v: R(0,0.785398)@q2, VZ(0.785398)@q2op 11 at T0_1h: R(1.5708,1.5708)@q0, MS(1.5708)@q0,q1, R(-1.5708,0)@q0, R(-1.5708,0)@q1, R(-1.5708,1.5708)@q0op 10 at T0_1v: R(1.5708,-1.5708)@q2, VZ(3.14159)@q2op 12 at T0_1h: R(0,0.785398)@q0, VZ(0.785398)@q0op 13 at T0_0v: R(0,2.35619)@q1, VZ(-0.785398)@q1op 14 at T0_1h: R(1.5708,1.5708)@q0, MS(1.5708)@q0,q1, R(-1.5708,0)@q0, R(-1.5708,0)@q1, R(-1.5708,1.5708)@q0
verdict · exact 8x8 unitary, built from the emitted pulses, against the circuit as written; global phase -1.5708
29 rules holdR10 holdsO1, proved checker: acceptedO2: ok (max entry error 1.12e-15)
open the page, with the circuit beside the programme
the machine: press Play, or step it
hardware programme (59 instructions, cooled)
#0   init q0@T0_1h, q1@T0_1v, q2@T0_0v
#1   cool all
#2   gate R q2 @T0_0v   ← op 0 h
#3   gate VZ q2 @T0_0v   ← op 0 h
#4   shuttle q1 T0_1v→T0_0v   ← op 1 cx
#5   gate R q1 @T0_0v   ← op 1 cx
#53  cool all
#6   gate MS q1,q2 @T0_0v   ← op 1 cx
#7   gate R q1 @T0_0v   ← op 1 cx
#8   gate R q2 @T0_0v   ← op 1 cx
#9   gate R q1 @T0_0v   ← op 1 cx
#10  shuttle q1 T0_0v→T0_1v   ← op 1 cx
#11  gate R q2 @T0_0v   ← op 2 tdg
#12  gate VZ q2 @T0_0v   ← op 2 tdg
#13  shuttle q2 T0_0v→T0_1h   ← op 3 cx
#14  gate R q0 @T0_1h   ← op 3 cx
#54  cool all
#15  gate MS q0,q2 @T0_1h   ← op 3 cx
#16  gate R q0 @T0_1h   ← op 3 cx
#17  gate R q2 @T0_1h   ← op 3 cx
#18  gate R q0 @T0_1h   ← op 3 cx
#19  gate R q2 @T0_1h   ← op 4 t
#20  gate VZ q2 @T0_1h   ← op 4 t
#21  shuttle q2 T0_1h→T0_1v   ← op 5 cx
#22  gate R q1 @T0_1v   ← op 5 cx
#55  cool all
#23  gate MS q1,q2 @T0_1v   ← op 5 cx
#24  gate R q1 @T0_1v   ← op 5 cx
#25  gate R q2 @T0_1v   ← op 5 cx
#26  gate R q1 @T0_1v   ← op 5 cx
#27  shuttle q1 T0_1v→T0_1h   ← op 8 t
#28  gate R q2,q1 @T0_1h,T0_1v   ← op 6 tdg, 8 t
#29  gate VZ q2,q1 @T0_1h,T0_1v   ← op 6 tdg, 8 t
#30  shuttle q0 T0_1h→T0_1v   ← op 7 cx
#31  gate R q0 @T0_1v   ← op 7 cx
#56  cool all
#32  gate MS q0,q2 @T0_1v   ← op 7 cx
#33  gate R q0 @T0_1v   ← op 7 cx
#34  gate R q2 @T0_1v   ← op 7 cx
#35  gate R q0 @T0_1v   ← op 7 cx
#36  shuttle q0 T0_1v→T0_1h   ← op 11 cx
#37  gate R q2,q0 @T0_1h,T0_1v   ← op 9 t, 11 cx
#38  gate VZ q2 @T0_1v   ← op 9 t
#57  cool all
#39  gate MS q0,q1 @T0_1h   ← op 11 cx
#40  gate R q0 @T0_1h   ← op 11 cx
#41  gate R q1 @T0_1h   ← op 11 cx
#42  gate R q0 @T0_1h   ← op 11 cx
#43  shuttle q1 T0_1h→T0_0v   ← op 13 tdg
#44  gate R q2,q0,q1 @T0_0v,T0_1h,T0_1v   ← op 10 h, 12 t, 13 tdg
#45  gate VZ q2,q0,q1 @T0_0v,T0_1h,T0_1v   ← op 10 h, 12 t, 13 tdg
#46  shuttle q1 T0_0v→T0_1h   ← op 14 cx
#47  gate R q0 @T0_1h   ← op 14 cx
#58  cool all
#48  gate MS q0,q1 @T0_1h   ← op 14 cx
#49  gate R q0 @T0_1h   ← op 14 cx
#50  gate R q1 @T0_1h   ← op 14 cx
#51  gate R q0 @T0_1h   ← op 14 cx
#52  shuttle q1 T0_1h→T0_1v   ← op 14 cx